1. Field of the Invention
This invention generally relates to digital communications and, more particularly, to a system and method for generating a frequency lock signal from a digital phase error message in phase-locked loop (PLL) applications.
2. Description of the Related Art
Digital PLLs (DPLLs) are an area of active research and development. A DPLL performs the loop filtering function in the digital domain with synthesized logic. DPLLs provide several advantages over the analog PLLs, including easier and faster implementation, and better controllability of the PLL parameters. Also, the integrated circuit (IC) die area devoted to the circuitry and power consumption can be greatly reduced, especially in advanced fabrication processes. Therefore, there is a growing interest in DPLLs for high performance applications.
FIG. 13 is a schematic block diagram of a fractional-N digital PLL (prior art). PLL clock synthesizers are ubiquitous in communication systems. Despite the popularity of the integer divider phase lock loop (PLL), fractional-N PLLs provide additional flexibility with the ratio of output clock frequency to reference clock frequency being a fraction rather than an integer. Conventional Fractional-N PLLs require a modulus divider, such that the average divide ratio of the feedback clock is a fraction, by modulating the divide ratio of a modulus divider. This divider modulation produces in-band modulation noise and requires PLL bandwidth to be low to filter out the in-band noise.
In a PLL based frequency synthesizer, the voltage controlled oscillator (VCO) clock is constantly compared with a reference clock. This comparison generates an error signal that is filtered and provided to the VCO, to correct the VCO frequency. In a charge pump PLL (CPPLL), a combination of phase/frequency detector (PFD) and charge pump perform phase error detection, and output an analog error signal. In DPLL, there is a need to convert this analog error signal to a digital error signal. One way of converting an analog signal to a digital signal is to utilize an analog-to-digital converter (A/D), but this approach requires additional power consumption and IC die area. A more practical approach would be to use a time-to-digital converter (TDC) to directly convert the phase offset to a digital error signal. A TDC can be used to digitize the duration of time between two events, usually represented by the edges of a signal. As described in more detail below, a TDC can be enabled with a delay line and sampling flip flops.
A key implementation challenge with the use of a TDC is the achievement a fine resolution error signal, in order to minimize the quantization noise effect on the PLL closed loop performance. However, a very fine resolution TDC usually has high power consumption, making it unattractive compared to conventional charge pump architecture. Therefore, a major challenge associated with a TDC is the tradeoff between resolution and power consumption. For example, a 155 megahertz (MHz) reference clock and 5 picoseconds (ps) of resolution require more than 210 delay elements/samplers.
It would be advantageous if a low-power TDC architecture could be used in DPLLs. To that end, the parent application entitled, SUCCESSIVE TIME-TO-DIGITAL CONVERTER FOR A DIGITAL PHASE-LOCKED LOOP, invented by Hanan Cohen et al, Ser. No. 12/841,131, filed Jul. 21, 2010, provides a TDC to replace a conventional PFD/charge pump in an analog PLL system. The TDC compares a reference clock to a frequency synthesizer feedback clock, and generates a digital word that represents the phase offset between the two.
In a typical PLL, an internal oscillator is calibrated such that its frequency is exactly identical to an external reference times a ratio. A DPLL consists of an oscillator which can be digitally calibrated. A mechanism is needed to detect the proximity of the oscillator frequency with respect to a target frequency. This mechanism is called lock detection.
A conventional lock detect system in an analog PLL monitors the reference clock (refclk) and a divided down version of the VCO (vcoclk), and generates an indication on the locking status of the PLL. In a DPLL system, a divided down version of the VCO clock may not always be available. Adding a high speed divider just for lock monitoring however, increases power consumption, and therefore should be avoided in low power applications.
It would be advantageous if a digital phase error signal could be used to quickly determine if a synthesizer frequency source is locked to a reference frequency.